Responsibilities

• Define SoC DfT architecture and DfM concept
• Implement and verify DfT measures to meet product specifications and production requirements
• Work closely with cross-function teams (design, production test and qualification) to meet test requirements with effective DfT solutions
• Achieve target coverage requirements for logic, memories, IO and mixed-signal IPs
• Generate test patterns and support post-silicon ATE and QnR
• Continue improving the DfT methods to optimize test time, IR-Drop and testability on internal and external IPs

Requirements

• Degree/Master in Electrical/Electronic Engineering
• 5 years or above experience in the area of DfT and RTL design field
• Expertise in ATPG scan, test controller, MBIST and their implementation
• Proficiency in HDL, synthesis, STA, top-level constraints and scripting
• Proficiency in EDA tools, e.g. VCS, TestMax DFT/ATPG/Advisor
• Strong analytical and problem solving skills
• Experience on volume production will be added advantage
• Open and collaborative working style